FIG. 1 depicts a small portion of a conventional magnetic random access memory (MRAM) 1. The conventional MRAM 1 includes a magnetic storage cell 10 having a conventional magnetic element 12 that is typically a conventional magnetic tunneling junction (MTJ) 12, and a conventional read selection transistor 14. Also depicted are a conventional write word line 16, a conventional read word line 18, and a conventional bit line 20. Data is stored in the conventional magnetic element 12 by programming the conventional magnetic element to be in a high resistance state or a low resistance state. This programming is typically performed by applying magnetic fields from current pulses flowing in both the conventional bit line 20 and the conventional write word line 16. The conventional magnetic element 12 is read by activating the read selection transistor 14 using the read word line 18 and driving a read current through the conventional magnetic element.
FIG. 2 depicts a larger portion of a conventional MRAM array 30 which uses multiple conventional memory cells, such as the conventional magnetic storage cell 10 depicted in FIG. 1. Referring back to FIG. 2, the conventional magnetic storage cells 10 are arranged in rows and columns. The conventional magnetic storage cells 10 are still associated with conventional read word lines 18, conventional write word lines 16, and conventional bit lines 20. Also depicted are bit line selector 32, word line selector 34, first digit line selector 36, second digit line selector 38, bit and ground line selector 40, differential current sensor with current sources 42, comparator 44, reference column 46 having storage cells 10′ corresponding to the storage cells 10 and bit line 22 corresponding to the bit lines 20, and switches 48, 50, 52, 54, 56, and 58. The conventional read word lines 18 are connected to the word line selector 34. Each conventional write word line 16, which may also be termed a digit line, is connected to first and second digit line selectors 36 and 38, respectively. Read word lines 18, and write word lines 16 run horizontally, while bit lines 20, which also serve as data lines, run vertically. The bit lines 20 are connected to first and second bit line selectors 32 and 40. The transistor switches 48, 50, 52, 54, 56, and 58, at the ends of the lines 16, 18, 20, and 22 connect the lines 16, 18, 20, and 22 to voltage sources, such as the power supply or ground.
During a write operation, a conventional bit line 20 supplying a portion of the magnetic field required for switching (termed the switching field) the magnetic element 12 is activated. In addition, a corresponding horizontal, conventional write word line 16 supplying remaining portion of the switching field is activated. Ideally, neither the magnetic field generated using the bit line 20 (bit line field), nor the magnetic field generated by the write word line 16 (digit line field) is alone sufficient to program any conventional magnetic element 12. However, in combination the bit line 20 and the write word line 16 can generate the switching field at their cross point. Consequently, a selected conventional magnetic element 12 can be written.
During a read operation, a conventional read word line 18 and a conventional bit line 20 containing the magnetic element to be read are activated. Only the conventional magnetic storage cell 10 at the cross point between the activated bit line 20 and the activated read word line 18 is read. The resistance state of the conventional magnetic storage cell being read is compared to the reference cell 10′ by the differential current sensor 42 and the comparator 44, which compares the two current signals and produces an output Vout for memory state “1” or “0”.
One of ordinary skill in the art will readily recognize that the conventional MRAM 30 using the conventional magnetic storage cell 10 has several drawbacks. During writing, magnetic storage cells 10 along the same conventional bit line 20 or the conventional write word line 16 as the magnetic storage cell 10 being written are also exposed to the bit line or digit line fields. These fields, coupled with a large distribution in the switching fields for conventional magnetic storage cells 10 in a large memory array 30, can cause unintentional error writing. As a result, performance of the conventional MRAM 10 suffers. This problem may be solved by using an advanced architecture called toggle writing. However, toggle writing requires much higher magnetic field, which utilizes a significantly higher current. This significantly increases the power consumption of the MRAM 10. Moreover, toggle writing requires a read verification prior to actual writing, thus making the total access time longer, making it unattractive for high speed embedded applications. The current generation memory cell size for conventional MRAM including toggle writing MRAM is close to 40F2 with F being the lithography critical dimension. They are competitive with semiconductor memory SRAM in density, yet MRAM may cost more since they use five to seven more masks than SRAM.
Furthermore, for the conventional magnetic element 12 written using an applied field, the current required to generate the switching field increases as the width of the conventional magnetic element 12 decreased. Consequently, power consumption is greatly increased, particularly for a smaller magnetic element 12 in a higher density memory. This increased power consumption is undesirable. A major drawback for conventional MRAM, including toggle writing MRAM, is its switching current scaling property. Consequently, another mechanism for providing an MRAM is desired.
FIG. 3 depicts a small portion of a conventional spin transfer torque random access memory (STT-RAM) 70. The STT-RAM 70 includes a conventional magnetic storage cell 80 including a conventional magnetic element 82 and a selection device 84 that is preferably an isolation transistor 84, word line 86, bit line 88, and source line 90. The word line 86 is oriented perpendicular to the bit line 88. However, the source line 90 is typically either parallel or perpendicular to the bit line 88, depending on specific architecture used for the STT-RAM 70.
The conventional magnetic element is typically a magnetic tunneling junction (MTJ) and is configured to be changeable between high and low resistance states by driving a spin polarized current through the conventional MTJ 82. The spin polarized current changes state of the conventional MTJ 82 using spin transfer torque switching effect. Typically, this is achieved by ensuring that the MTJ 82 has a sufficiently small cross-sectional area and that the layers of the MTJ have particular thicknesses. When the current density is sufficient, the current carriers driven through the conventional magnetic element 82 may impart sufficient torque to change the state of the conventional magnetic element 82. When a write current is driven in one direction, the state may be changed from a low resistance state to a high resistance state. When the write current is driven in the opposite direction, the state may be changed from a high resistance state to a low resistance state.
In order to program the conventional storage cell 80, the bit line 88 and the word line 86 are activated. A current is driven between the source line 90 and the bit line 88. To program the conventional MTJ 82 to a first state, a high voltage is supplied to the bit line 88 and a low voltage, such as ground, is supplied to the source line 90. Thus, the write current passes from the bit line 88 to the conventional MTJ 82 and then the source line 90. To program the conventional MTJ 82 to a second state, a high voltage is supplied to the source line 90 and a low voltage, such as ground, is supplied to the bit line 88. Thus, the write current passes from the source line 90 to the conventional MTJ 82, and then the bit line 88.
For a read operation, the bit line 88 and the word line 86 are activated. Consequently, the selection device 84 is turned on. A read current is driven through the conventional magnetic element 82. The read current may be provided by a differential current sensor analogous to the differential current sensor 42 depicted in FIG. 2. Referring back to FIG. 3, the read current is thus provided to the bit line 88, which may have its bias voltage clamped. As a result, a high magnetoresistive signal can be obtained during sensing. In some conventional spin RAM, a reference cell (not shown in FIG. 3) may be used. In such a conventional spin RAM, a portion of the read current is provided to the conventional magnetic storage cell 80 being read and a portion of the current is provided to the reference cell. Thus, the current being sensed during a read operation is the difference between a constant supply current and the current that actually flows through the MTJ element. A comparator that is analogous to the comparator 44 of FIG. 2, compares the output of the differential current sensor to determine the state of the conventional magnetic storage cell 80. Thus, the conventional magnetic storage cell 80 can be programmed and read.
Thus, the conventional spin RAM 70 utilizes a write current driven through the magnetic element 82 in order to program data to the conventional magnetic storage cell 80. Thus, the conventional spin RAM 70 uses a more localized phenomenon in programming the conventional magnetic element 82. Furthermore, for smaller magnetic elements 82 and, therefore, higher memory densities, the conventional spin RAM 70 uses a lower current.
FIG. 4 is a graph 92 depicting a comparison between the write current for the conventional magnetic field switched MRAM 30 and for the conventional STT-RAM 70. Note that the write current for toggle writing MRAM is higher than the current in FIG. 4. For a conventional magnetic MTJ 12/82 having width less than two hundred nanometers, the current required for the conventional STT-RAM 70 is lower than that for conventional MRAM 30 and keeps decreasing as width decreases, of example for future generation technology. This is in contrast to the conventional MRAM 30, which has a write current that increases as the dimensions of the conventional MTJ 12 shrinks. Toggle writing for the conventional MRAM 30 requires even higher writing currents than conventional MRAM. Higher writing current means higher power consumption, larger memory cell and memory chip size and more reliability problems such as electro-migration. Thus STT-RAM 70 has the desired current scaling trend. Moreover, unlike conventional MRAM 30, the conventional STT-RAM 70 does not suffer from a half select write disturb problem because the conventional STT-RAM 70 is written by a current flowing only through the cell 80 being written.
FIG. 5 is a graph 94 depicting write and read current distributions. Although the conventional STT-RAM 70 does not have a half select write disturb problem, there may be read disturb issues which may be illustrated in FIG. 5. The current distribution 96 is a write current distribution for switching the antiparallel (high resistance) state of the magnetic element 82 to the parallel (low resistance) state of the magnetic element 82. The current distribution 95 is a write current distribution for switching from the parallel state of the conventional magnetic element 82 to the antiparallel state of the conventional magnetic element 82. The current distribution 97 is the read current distribution for the parallel or low resistance state. The current distribution 98 is the read current distribution for the antiparallel or high resistance state. In addition, a conventional STT-RAM 70 has not one, but many magnetic storage cells 80. Process variations may cause the write and read currents of the magnetic elements 82 within a conventional spin RAM 70 to have a distribution range. Consequently, the distributions 95, 96, 97, and 98 are depicted as having a range. Moreover, each write current distribution 95 and 96 has a minimum write current I1 and I2, respectively. In general, most memory cells may be written at write currents above the currents I1 or I2. Furthermore, each read current distribution 97 and 98 has a maximum read current I3 and I4, respectively. Most cells can be read for read currents less than I3 or I4. However, it may be noted that there may be a few magnetic storage cells 80 that may not be written to the antiparallel state at currents outside of the distribution 95 as well as magnetic storage cells 80 that may not be written to the parallel state even at currents outside of the distribution 96. These magnetic storage cells 80 are called tail distribution bits, or outliers. In general, the difference between the maximum reading current 13 or 14 and the minimum writing current I1 or I2 represents the reading and writing margin.
High speed memory operation requires high read current difference between the two different memory states. The state of the art magnetic element 82 has a magnetoresistance (MR) ratio of approximately one hundred to one hundred fifty percent at an operating voltage range of approximately one hundred fifty to five hundred millivolts. Therefore, high read current difference comes from a high read current and a high MR ratio. As discussed above, a smaller transistor 84 would require a lower STT-RAM write current. Consequently, the difference between write currents 95 and 96 and read currents 97 and 98 is narrowed for higher density STT-RAMs 70 having smaller cell 80 sizes as well as for higher speed and larger read signals. In addition to process variation caused distribution, thermal effects may also cause variations in read and/or write currents. During the full life of a Mega- to Giga-bits memory chip operation, even a much lower read current 97 or 98 may accidentally switching or writing a bit due to thermal assisted switching. Consequently, the write and read margins may be even smaller. Thus, the possibility of data being compromised during a read operation might be even further increased.
In addition to reduced write and read margins for the conventional STT-RAM 70, to realize the potential benefits of the conventional STT-RAM 70 and allow this technology to be competitive with general semiconductor memory such as SRAM, DRAM and Flash, a number of parameters are desired to be optimized for STT-RAM. The writing current of conventional STT-RAM 70 is desired to be reduced further. A lower write current allows a smaller isolation transistor 84 per magnetic storage cell 80 to control the write current. Consequently, a smaller magnetic storage cell 80, and a higher density memory may be provided.
Accordingly, what is desired is a method and system for providing and utilizing memory cells employing spin transfer based switching with improved read and write margin, or reduced reading current induced accidental writing error. The present invention addresses such a need.